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CREATED:20120515T130232Z
DESCRIPTION:In Quest of a Fast\, Low-Voltage Digital Switch\n\nThomas N. Th
eis\nProgram Manager\, New Devices and Architectures for Computing \nIBM T
.J. Watson Research Center\n \n Thursday\, May 31\, 2012 10:30AM - 11
:30AM\, Building 215\, Room C103-106\n Because the performance of today’
s computational systems is severely constrained by economic limits on allo
wable power dissipation\, reduced dissipation in device switching may be t
he most critical attribute for the success of any new switch which can rep
lace the field effect transistor for digital logic. There are two broad an
d very distinct physical approaches to reduced power dissipation. The firs
t approach is to store less energy in the device to distinguish digital lo
gic states. The second approach is to conserve the stored energy from swit
ching event to switching event by implementing near-adiabatic switching pr
otocols and energy-conserving logic circuits. In this talk\, I focus on th
e first approach\, and further limit the discussion to three-terminal\, vo
ltage-controlled current switches – devices which should be broadly comp
atible with silicon interconnection technology and with well-established F
ET circuit families. I discuss several classes of proposed low-voltage dev
ices\, and identify the underlying operating principles which enable those
devices to overcome the voltage-scaling limit of the conventional field e
ffect transistor. I argue that the operating principles exemplified by the
se devices are quite general\, and can be applied in ways that have not ye
t been explored. It is therefore likely that we are still in the early sta
ges of the quest for a fast\, low-voltage digital switch.\n \n S
ponsor: Fred Sharifi\, 301-975-4633\, fred.sharifi@nist.gov\n\n\n
DTEND;TZID="Eastern Standard Time":20120531T113000
DTSTAMP:20120515T130232Z
DTSTART;TZID="Eastern Standard Time":20120531T103000
LAST-MODIFIED:20120515T130232Z
LOCATION:Bldg.215/Rm.C103-106
PRIORITY:5
SEQUENCE:0
SUMMARY;LANGUAGE=en-us:CNST Nanotechnology Seminar Series - Thomas N. Theis
- In Quest of a Fast\, Low-Voltage Digital Switch
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ENTER><SPAN LANG="en-us"><B><I></I></B></SPAN><SPAN LANG="en-us"><B><I></I
></B></SPAN><SPAN LANG="en-us"><B><I></I></B></SPAN><B><I><SPAN LANG="en">
<FONT COLOR="#000000" FACE="Times New Roman">In Quest of a Fast\, Low-Volt
age Digital Switch</FONT></SPAN></I></B><SPAN LANG="en-us"><I></I></SPAN><
SPAN LANG="en-us"><I></I></SPAN><SPAN LANG="en-us"><I></I></SPAN><I><SPAN
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"Times New Roman">Thomas N. Theis</FONT></SPAN></I></B><SPAN LANG="en-us">
<I></I></SPAN><SPAN LANG="en-us"><I></I></SPAN><SPAN LANG="en-us"><I></I><
/SPAN><I><SPAN LANG="en"></SPAN></I></P>\n\n<P DIR=LTR ALIGN=CENTER><SPAN
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<SPAN LANG="en-us"><B><I></I></B></SPAN><B><I><SPAN LANG="en"><FONT COLOR=
"#000000" FACE="Times New Roman">Program Manager\, New Devices and Archite
ctures for Computing</FONT></SPAN></I></B><SPAN LANG="en-us"><I></I></SPAN
><SPAN LANG="en-us"><I></I></SPAN><SPAN LANG="en-us"><I></I></SPAN><I><SPA
N LANG="en"> </SPAN></I></P>\n\n<P DIR=LTR ALIGN=CENTER><SPAN LANG="en-us"
><B><I></I></B></SPAN><SPAN LANG="en-us"><B><I></I></B></SPAN><SPAN LANG="
en-us"><B><I></I></B></SPAN><B><I><SPAN LANG="en"><FONT COLOR="#000000" FA
CE="Times New Roman">IBM T.J. Watson Research Center</FONT></SPAN></I></B>
<SPAN LANG="en-us"><I></I></SPAN><SPAN LANG="en-us"><I></I></SPAN><SPAN LA
NG="en-us"><I></I></SPAN><I><SPAN LANG="en"></SPAN></I></P>\n<UL DIR=LTR><
UL DIR=LTR><UL DIR=LTR>\n<P DIR=LTR><SPAN LANG="en-us"></SPAN><SPAN LANG="
en-us"></SPAN><SPAN LANG="en-us"></SPAN><SPAN LANG="en"><FONT COLOR="#0000
00" FACE="Times New Roman"> </FONT></SPAN><SPAN LANG="en-us"></SPAN><SPAN
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\n\n<P DIR=LTR ALIGN=CENTER><SPAN LANG="en-us"></SPAN><SPAN LANG="en-us"><
/SPAN><SPAN LANG="en-us"></SPAN><SPAN LANG="en"><FONT COLOR="#000000" FACE
="Times New Roman">Thursday\, May 31\, 2012 10:30AM - 11:30AM\, Building 2
15\, Room C103-106</FONT></SPAN><SPAN LANG="en-us"></SPAN><SPAN LANG="en-u
s"></SPAN><SPAN LANG="en-us"></SPAN><SPAN LANG="en"></SPAN></P>\n</UL></UL
></UL>\n<P DIR=LTR ALIGN=JUSTIFY><SPAN LANG="en-us"><B></B></SPAN><SPAN LA
NG="en-us"><B></B></SPAN><SPAN LANG="en-us"><B></B></SPAN><B><SPAN LANG="e
n"><FONT COLOR="#000000" FACE="Times New Roman"> </FONT></SPAN></B><SPAN
LANG="en-us"></SPAN><SPAN LANG="en-us"></SPAN><SPAN LANG="en-us"></SPAN><S
PAN LANG="en"><FONT COLOR="#000000" FACE="Times New Roman">Because the per
formance of today’\;s computational systems is severely constrained b
y economic limits on allowable power dissipation\, reduced dissipation in
device switching may be the most critical attribute for the success of any
new switch which can replace the field effect transistor for digital logi
c. There are two broad and very distinct physical approaches to reduced po
wer dissipation. The first approach is to store less energy in the device
to distinguish digital logic states. The second approach is to conserve th
e stored energy from switching event to switching event by implementing ne
ar-adiabatic switching protocols and energy-conserving logic circuits. In
this talk\, I focus on the first approach\, and further limit the discussi
on to three-terminal\, voltage-controlled current switches –\; device
s which should be broadly compatible with silicon interconnection technolo
gy and with well-established FET circuit families. I discuss several class
es of proposed low-voltage devices\, and identify the underlying operating
principles which enable those devices to overcome the voltage-scaling lim
it of the conventional field effect transistor. I argue that the operating
principles exemplified by these devices are quite general\, and can be ap
plied in ways that have not yet been explored. It is therefore likely that
we are still in the early stages of the quest for a fast\, low-voltage di
gital switch.</FONT></SPAN><SPAN LANG="en-us"></SPAN><SPAN LANG="en-us"></
SPAN><SPAN LANG="en-us"></SPAN><SPAN LANG="en"></SPAN></P>\n\n<P DIR=LTR><
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p\; \; \; \; \; \; \;</SPAN><SPAN LANG="en-us"></S
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sp\; \; \; \;  \; \; \; \; \; \; \
;  \; \; \; \; \; \; \;  \; \; \;&
nbsp\; \; \; \;  \; \; \; \; \; \;&nbs
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PAN><SPAN LANG="en-us"><FONT FACE="Times New Roman">Sponsor: Fred Sharifi\
, 301-975-4633\, fred.sharifi@nist.gov</FONT></SPAN><SPAN LANG="en-us"></S
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utorak, 15. svibnja 2012.
NANOTEHNOLOGY
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